1. Field of the Invention
The present invention relates to a multi-value type semiconductor memory device and its defect removal method.
2. Prior Art
To enhance the production yield, many semiconductor memory devices incorporating ECC (Error Correcting Code) circuits as means of saving from defective bits have been proposed and used, and are greatly contributing to mass production.
On the other hand, there is an increasing demand for larger memory capacity, and various memory devices of multi-value type having a double capacity of the conventional memory cell by writing two-bit information in one memory cell have been proposed.
FIG. 1 is a block diagram of an example of using ECC circuit as defective bit removal method in a conventional multi-value type memory. In the diagram, in this cell 5, data is written in multi-value system, and it is supposed that two-bit information is written in one memory cell. As this method of writing, hitherto, several methods have been disclosed, and it is supposed herein that the threshold level of the memory cell is adjusted. More specifically, the two-bit data is data worth two words for one output bit, and the data held in a latch circuit 1 is selected by a page changeover signal p, and data D1 and D2 are outputted from an output circuit 8.
On the other hand, in an ECC cell 7, data is written in multi-value system, and the data written in this ECC cell 7 is written according to the ECC method known well as Hamming code. Generally, for n-bit data length, the number of parity bits P necessary for detecting and correcting an error of one bit is expressed in the following formula (1). EQU 2P.gtoreq.(n+1) (1)
For example, in the case of an output data length of four bits, the number of parity bits required for detecting and correcting an error of one bit is 3 bits.
Herein, referring to FIG. 1, the operation of this circuit is described below. In this cell 5, a multi-value level written in the memory cell by two sense amplifiers 4 is read by three data lines, and these three pieces of data are sent into a binary conversion circuit 3, and they are converted into two-bit data individually in this binary conversion circuit 3. Now, the bit length to be corrected is 4 bits, which requires 3 bits of parity. Accordingly, the ECC cell 7, same as this cell 5, has two sense amplifiers, and four-bit data is outputted from the binary conversion circuit 3. At this time, one piece of output data is unnecessary data. By entering four bits of conversion data of this cell 5 and three bits of conversion data of the ECC cell 7 into the ECC circuit 6, an error is detected, and an error correction signal is generated. The error correction signal is put into an error correction circuit 2 corresponding to each output, and only the data of the output bit in which error is detected is corrected, and all data is held in a latch circuit 1.
The binary conversion circuit 3, correction circuit 2, and ECC circuit 6 used in this circuit are described below while referring to FIGS. 2A and 2B, 3 and 4, respectively. FIG. 2A is a diagram showing correspondence of multi-value level and binary data for converting four-value level into binary data, as an example of the binary conversion circuit 3, and FIG. 2B is a circuit diagram of its conversion circuit.
When writing two-bit data by controlling the threshold of the memory cell and writing data, as shown in FIG. 2A, gate voltages Vg1 to Vg3 sequentially applies three gate voltage levels Vg, for reference voltages Vt0, Vt1, Vt2, Vt3, in the relation of Vt0&lt;Vg1&lt;Vt1&lt;Vg2&lt;Vt2&lt;Vg3&lt;Vt3.
First, when gate voltage Vg1 is applied, the cells written at reference voltage Vt0 are turned on, but other cells written at other threshold remain in off state at this stage. Next, when the level is changed to gate voltage Vg2, the cells written at reference voltage Vt0, Vt1 are turned on, but other cells written at other threshold remain in off state. When changed to the level of gate voltage Vg3, similarly, all cells but cells written at reference voltage Vt3 are turned on.
Herein, FIG. 2A shows the correspondence between this state and the data of output bits, in which multi-value levels of the memory cells are read out in three data lines (1 to 3) by the sense amplifier 4, and converted into two-bit higher and lower digit data by the binary conversion circuit 3. That is, when all data lines 1 to 3 are 0, the higher and lower digit data are 00, when data lines 1 to 3 are 100, higher and lower digit data are 01, . . . , and when data lines 1 to 3 are 111, higher and lower digit data are 11.
In this case , the binary conversion circuit 3 is composed of inverter 35, and NAND circuits 36 to 38 as shown in FIG. 2B, data 2 is lower digit data, and the logic output by NAND 36 to 38 of data 1, 3 and data 2, and its inverted output is the higher digit data.
The correction circuit 2 is composed of an exclusive OR (EOR) 20 as shown in a circuit diagram in FIG. 3, and correction signals D1, 2 from the ECC circuit 6 are entered in one input of the EOR 20, and data from the binary conversion circuit 3 is entered in other input, and when the correction signals D1, 2 are 1, the input data is inverted and outputted, and when the correction signals D1, 2 are 0, the input data is directly outputted.
Further, the ECC circuit 6 comprises, as shown in a circuit diagram in FIG. 4, OR 101 to 103 for calculating the OR logic of parity data 0 to 2 and the higher and lower digit data of sense amplifier 4 (0,1), NAND 111 to 114 for calculating the NAND of these OR outputs and outputs of their outputs through inverters 104 to 110, and OR 115 to 118 for calculating the OR of these outputs of the NAND 111 to 114 and the higher and lower digit data of sense amplifier 4 (0,1), and outputs of the OR 115 to 118 are correction outputs.
In the multi-value type memory explained above, the operation timing is summarized in the operation waveform diagram in FIG. 5. First, lower digit data and lower digit parity data to which the data is directly outputted are entered, and higher digit data and high digit parity data are entered from the binary conversion circuit 3 at time t11, and at this time, a correction signal is outputted (t12), and correction output data from the correction circuit 2 is obtained (t13), then by its output, a latch control signal P is outputted, and the terminal point (t14) is the latch timing of upper/lower digit data.
In this multi-value type memory, however, there is a problem in the data conversion timing of multi-value type memory. That is, same as in the prior art, when writing two-bit data by controlling the threshold of the memory cell and writing data in, three levels Vg are sequentially applied in the relation of Vt0&lt;Vg1&lt;Vt1&lt;Vg2&lt;Vt2&lt;Vg3&lt;Vt3, but in the multi-value type memory, since it is required to detect the changes of these three stages by the sense amplifier 4 and convert into two-bit data in the binary conversion circuit 3, output cannot be outputted to outside until all data is established (t11 in FIG. 5), and error correction by the ECC circuit 2 cannot be done. As a result, the access time is long.
Besides, if the defective bit removal method by the ECC circuit 2 is applied in this multi-value type memory, as compared with the ordinary cell system, the saving rate is lowered. The reason is as follows: in the ordinary memory cell of one bit and one cell system, the data being read out from one bit of memory cell is either 1 or 0, and if there is one defective memory cell, in case one bit is defective, the error can be corrected by the ECC circuit. By contrast, in the multi-value type memory, if defect occurs in one memory cell, the data being read out from one memory cell is a plurality, and therefore if one memory cell is defective, plural pieces of data may be defective, and hence the defective bit may not be removed by the ECC circuit 2.